Knowledge and Data Management White Papers
Modeling of Jitter in Bang-Bang Clock and Data Recovery Circuits
Overview Clock and Data Recovery (CDR) circuits incorporating bang-bang (binary) Phase Detectors (PDs) have recently found wide usage. In contrast to their linear counterparts, bang-bang PDs relax the speed and precision required of flipflops and other circuits in the signal path, reducing the complexity and the power dissipation. However, the heavily nonlinear nature of these PDs makes the loop analysis difficult. This paper describes an approach to modeling bang-bang CDR loops with emphasis on jitter characteristics. The methodology predicts jitter transfer, tolerance, and generation as well as the Bit Error Rate (BER). A 1-Gb/s CMOS CDR circuit is designed and fabricated as an experimental vehicle to validate the predictions.
| Publisher | University of California | File Format | |
|---|---|---|---|
| Date Published | April 2005 | ||
| Format | White Papers | ||
| Topics | |||
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