Knowledge and Data Management White Papers
A 1O-Gb/s CMOS Clock and Data Recovery Circuit
Overview Clock and Data Recovery (CDR) circuits operating in the 1O-Gb/s range have become attractive for the optical fiber backbone of the Internet. While CDR circuits operating at 10-Gbls and above have been designed in bipolar technologies [I]-, cost and integration issues make it desirable to implement these circuits in standard CMOS processes. This paper describes the design and experimental results of a 1O-Gb/s CDR circuit that is realized in 0.18-?m CMOS technology. The speed limitations of the technology are overcome by the CDR architecture. The circuit produces a 5-GHz clock with an rms jitter of 6.6 ps in response to a random data input of length 223-1 while consuming 99 mW from a 2.6-V supply.
| Publisher | Institute of Electrical and Electronics Engineers | File Format | |
|---|---|---|---|
| Date Published | January 2003 | ||
| Format | White Papers | ||
| Topics | |||
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