Knowledge and Data Management White Papers
A Multiple-Rotating-Clock-Phase Architecture for Digital Data Recovery Circuits Using Verilog-A
Overview This paper presents an oversampling Data Recovery (DR) architecture using Verilog-A that employs a novel Multiple-Rotating-Clock-Phase (MRCP) concept for its operation. The MRCP-DR architecture is a variant of the eye-tracking DR architecture. Multiple rotating clock phases, supplied by a Delay-Locked Loop (DLL), establish a window for detecting data edges. As a result, the window width becomes robust against Process, Voltage and Temperature (PVT) variations. The MRCP architecture is tolerant of jitter on the local, blind, free-running oscillator that operates at approximately the incoming data frequency. Behavioral blocks are described and functional simulations are presented using the Verilog-A/Spectre/Cadence platform. The Verilog-A test benches allow the designer to perform system-level what-if analyses and make area, power and performance estimates.
| Publisher | Institute of Electrical and Electronics Engineers | File Format | |
|---|---|---|---|
| Date Published | October 2005 | ||
| Format | White Papers | ||
| Topics | |||
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