Bandwidth Issues White Papers
Efficient Use of Memory Bandwidth to Improve Network Processor Throughput
Overview This paper considers the efficiency of packet buffers used in packet switches built using Network Processors (NPs). Packet buffers are typically implemented using DRAM, which provides plentiful buffering at a reasonable cost. The problem addressed in this paper is that a typical NP workload may be unable to utilize the peak DRAM bandwidth. Since the bandwidth of the packet buffer is often the bottleneck in the performance of a shared-memory packet switch, inefficient use of available DRAM bandwidth further reduces the packet throughput. Specialized hardware-based schemes that alleviate the DRAM bandwith problem in high-end routers may be less applicable to NP-based systems, in which cost is an important consideration.
| Publisher | Purdue University | File Format | |
|---|---|---|---|
| Date Published | January 2008 | ||
| Format | White Papers | ||
| Topics | |||
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