Network Security White Papers
High-Throughput Linked-Pattern Matching for Intrusion Detection Systems
Overview This paper presents hardware architecture for highly efficient intrusion detection systems. In addition, a software tool for automatically generating the hardware is presented. Intrusion detection for network security is a compute-intensive application demanding high system performance. By moving both the string matching and the linking of multi-part rules to hardware, the architecture leaves the host system free for higher-level analysis. The tool automates the creation of efficient Field Programmable Gate Array architectures (FPGA). The generated hardware allows an FPGA-based system to perform deep-packet inspection of streams at up to 10 Gb/s line rates at a high level of area efficiency. Going beyond previous basic string-matching implementations that offer only single-string matching, the architecture provides support for rules requiring complex, linked (correlated-content) constructions.
| Publisher | Association for Computing Machinery | File Format | |
|---|---|---|---|
| Date Published | October 2005 | ||
| Format | White Papers | ||
| Topics | |||
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