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Network Security White Papers

Pattern Reduction and Circuit Design for Hardware-Supported Network Intrusion Detection

Tags:
network security

Overview Intrusion Detection Systems (IDS) suffer from be being overloaded as network rates increase. One of the performance bottlenecks in a multi-level packet inspection IDS is the computationally intensive task of pattern matching. Attackers can take advantage of this bottleneck by "Blinding" it with innocuous traffic and try to slip the attack traffic by the system without detection. It is also possible to perform a Denial-of-Service on the network if the IDS drops packets that are not inspected. These scenarios are possible since the IDS is busy examining the traffic intended to keep it busy and it becomes incapable of examining all packets. A more benign circumstance is the IDS needs simply to keep pace with current high-speed network traffic.

Further White Paper Details
Publisher	Institute of Electrical and Electronics Engineers	File Format	PDF
Date Published	May 2005
Format	White Papers
Topics	Network Security, Security Tools, Intrusion Detection Systems

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