Data Center White Papers
Datacenter-on-Chip Architectures: Tera-Scale Opportunities and Challenges
Overview The world has entered in an era of Chip MultiProcessor (CMP) platforms, where performance is delivered with the integration of more and more cores on a die. Tera-scale CMP architectures, consisting of several tens of physical cores and hundreds of hardware threads, are highly suitable for throughput computing especially in the server market place. This paper starts by highlighting tera-scale potential in datacenter environments. It shows how a multi-tier datacenter workload that required tens (to hundreds) of platforms in the past can potentially map on to one (or a few) single-socket tera-scale CMP platforms running Virtual Machines (VMs) and thereby creating Datacenter-on-Chip (DoC) architectures.
| Publisher | Intel | File Format | |
|---|---|---|---|
| Date Published | August 2007 | ||
| Format | White Papers | ||
| Topics | |||
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