Parallel Processing White Papers
Mesh-of-Trees and Alternative Interconnection Networks for Single-Chip Parallel Processing
Overview Many applications have stimulated the recent surge of interest single-chip parallel processing. In such machines, it is crucial to implement a high-throughput low-latency interconnection network to connect the on-chip components, especially the processing units and the memory units. This paper proposes a new Mesh of Trees (MoT) implementation of the interconnection network and evaluates it relative to metrics such as wire area, register count, total switch delay, maximum throughput, latency-throughput relation and delay effects of long wires. The paper shows that on-chip interconnection networks can facilitate higher bandwidth between processors and shared first-level cache than previously considered possible. This has significant impact for chip multiprocessing.
| Publisher | University of Maryland | File Format | |
|---|---|---|---|
| Date Published | August 2006 | ||
| Format | White Papers | ||
| Topics | |||
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