Embedded Systems White Papers
Integration of High-Performance Transistors, High-Density SRAMs, and 10-Level Copper Interconnects Into a 90 nm CMOS Technology
Overview This paper presents a 40 nm-gate-length transistor, an ultra-high-density 6T SRAM cell, 10-level Cu interconnects, and Very-Low-K (VLK) dielectrics for high-performance microprocessor applications. The key process features are 193 nm lithography with a Phase Shift Mask (PSM) and Optical Proximity Correction (OPC) that enables to fabricate a 40 nm-long gate and a sub-1 µm 2 SRAM cell, a unique transistor feature called a sidewall-notched gate that enables optimal pocket implant placement and suppresses variations of the notch width much better than a poly-notched gate structure, a 1.1 nm-thick nitrided oxide to achieve a high drive current and a reduced thermal budget to suppress boron penetration.
| Publisher | Fujitsu | File Format | |
|---|---|---|---|
| Date Published | June 2003 | Downloads | 1 |
| Format | White Papers | ||
| Topics | |||
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