Parallel Processing White Papers
Layout-Accurate Design and Implementation of a High-Throughput Interconnection Network for Single-Chip Parallel Processing
Overview A Mesh of Trees (MoT) on-chip interconnection network has been proposed recently to provide high throughput between memory units and processors for single-chip parallel processing. This paper reports the findings in bringing this concept to silicon. Specifically, it conducts cycle-accurate verilog simulations to verify the analytical results. The paper synthesizes and obtains the layout of the MoT interconnection networks of various sizes. To further improve throughput, the paper investigates different arbitration primitives to handle load and store, the two most common memory operations. The paper also studies the use of pipeline registers in large networks when there are long wires. Simulation based on full network layout demonstrates that significant throughput improvement can be achieved over the original proposed MoT interconnection network.
| Publisher | University of Maryland | File Format | |
|---|---|---|---|
| Date Published | June 2007 | ||
| Format | White Papers | ||
| Topics | |||
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