Local Area Networks (LAN) White Papers
High Speed Switch Scheduling for Local Area Networks
Overview Current technology trends make it possible to build communication networks that can support high performance distributed computing. This paper describes issues in the design of a prototype switch for an arbitrary topology point-to-point network with link speeds of up to one gigabit per second. The switch deals in fixed-length ATM-style cells, which it can process at a rate of 37 million cells per second. It provides high bandwidth and low latency for datagram traffic. In addition, it supports real-time traffic by providing bandwidth reservations with guaranteed latency bounds. The key to the switch's operation is a technique called parallel iterative matching, which can quickly identify a set of conflict-free cells for transmission in a time slot.
| Publisher | University of California | File Format | |
|---|---|---|---|
| Date Published | August 2006 | ||
| Format | White Papers | ||
| Topics | |||
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