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Modeling Wire Delay, Area, Power, and Performance in a Simulation Infrastructure
Overview IBM present Justice, a set of extensions to the Liberty simulation infrastructure that model chip area, wire length, and power consumption. Based on an architectural specification of a processor, Justice estimates the area and per-access power consumption of each module in the architecture. It then constructs a floorplan for the processor and computes the length and delay of critical communication paths. Finally, Justice modifies the architectural specification to account for wire delay and generates an executable simulator for the processor. To illustrate its capabilities, the authors simulate a number of Very Long Instruction Word (VLIW) architectures.
| Publisher | IBM | File Format | |
|---|---|---|---|
| Date Published | March 2006 | Downloads | 1 |
| Format | White Papers | ||
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