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Architectural Extensions and Optimizations in the PCIe PHY Layer

Overview The intended audience for this presentation is of platform architects and PHY Design engineers. Through this presentation, one can understand the speed change process and PCIe architectural extensions to help save power. The presentation explains PCIe specification enhancements for higher reliability/availability; PCIe specification enhancements for improved yield; improved compliance testing mechanism and design optimization and validation hints for the next generation of PCIe products.

Further White Paper Details
Publisher	Intel	File Format	PDF
Date Published	March 2006	Downloads	248
Format	Presentations
Topics	Network Design, Network Interface Cards

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