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Managing Risk in Block Based Designs: A Front End Acceptance Methodology

Overview It has recently become commonly accepted knowledge that System on Chip designs are tending to use more and more pre-built IP blocks as the most common way to achieve more reuse and faster time to markets. However, as most designers who have attempted this approach, will substantiate, this approach has lots of pitfalls and unforeseen risks. This paper outlines a very formal, step-by-step process or methodology by which design specifications as well as component blocks are analyzed for correctness, completeness and feasibility even before the design is started. This process is used as a way to quantify risk very early in the design phase. Having analyzed the data and understood the risks, design teams will be better suited to improve predictability.

Further White Paper Details
Publisher	Cadence Design Systems	File Format	PDF
Date Published	April 2006
Format	White Papers
Topics	N/A

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