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A Dual-Band-Enhanced Harmonic Rejection Filter for Modulators in GSM and DCS Transmitters

Overview In this paper, a dual-band enhanced harmonic rejection filter along with a quadrature modulator is designed and fabricated in 0.25µm CMOS process. This filter is simply a Sallen-Key low pass filter with transmission zeros to provide additional harmonic rejection. The measurement results show that the filter significantly suppresses the unwanted harmonics generated by the modulator by more than 30dB and 40dB in GSM mode and DCS mode, respectively. This IC operates at 2.7V with current consumption of 4.8mA and 5.7mA in GSM and DCS mode, respectively.

Further White Paper Details
Publisher	Industrial Technology Research Institute	File Format	PDF
Date Published	April 2003
Format	White Papers
Topics	N/A

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