White Papers

Low Complexity System-on-Chip Architectures of Parallel-Residue-Compensation in CDMA Systems

• Tags:
• interference cancellation,
• parallel,
• multi,
• stage

Overview This paper proposes a novel multi-stage Parallel-Residue-Compensation (PRC) receiver architecture for enhanced suppression of the MAI in CDMA systems. The commonality is extracted to avoid the direct Interference Cancellation and reduce the algorithm complexity from O (K2N) to O (KN). In the second part, scalable VLSI architectures are implemented in an FPGA prototyping system with an efficient Precision-C based System-on-Chip (SOC) design methodology. The design of Sum-Sub-MUX Unit (SMU) combinational logic avoids the usage of dedicated multipliers with at least 10X saving in hardware resources.

• 
• Did you find this white paper useful?

• Subscribe to the IT White Papers Newsletter
• White Paper RSS