Scalability White Papers
Micro-Architecture Techniques in the Intel E8870 Scalable Memory Controller
Overview This paper describes several selected micro-architectural tradeoffs and optimizations for the scalable memory controller of the Intel E8870 chipset architecture. The Intel E8870 chipset architecture supports scalable coherent multiprocessor systems using 2 to 16 processors, and a point-to-point Scalability Port (SP) Protocol. The scalable memory controller micro-architecture applies a number of micro-architecture techniques to reduce the local & remote idle and loaded latencies. The performance optimizations were achieved within the constraints of maintaining functional correctness, while reducing implementation complexity and cost.
| Publisher | Intel | File Format | PDF, requires Acrobat Rdr 5 |
|---|---|---|---|
| Date Published | June 2004 | Downloads | 17 |
| Format | White Papers | ||
| Topics | |||
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