Memory Components White Papers
Scalable Hardware Memory Disambiguation for High ILP Processors
Overview This paper describes several methods for improving the scalability of memory disambiguation hardware for future high ILP processors. As the number of in-flight instructions grows with issue width and pipeline depth, the load/store queues (LSQ) threaten to become a bottleneck in both power and latency. By employing lightweight approximate hashing in hardware with structures called Bloom filters many improvements to the LSQ are possible.
| Publisher | University of Texas at Austin | File Format | PDF, requires Acrobat Rdr 5 |
|---|---|---|---|
| Date Published | October 2003 | Downloads | 21 |
| Format | White Papers | ||
| Topics | |||
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