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Architecture and Design of a Simultaneously Bidirectional Single-Ended High Speed Chip-to-Chip Interface

Overview This paper presents the architecture, circuit techniques, and test results for a single-ended simultaneously bidirectional interface capable of a total throughput of 8 Gigabits per second per pin. The interface addresses the noise reduction challenges by utilizing a pseudo-differential reference with noise immunity approaching that of a fully differential reference. Furthermore, noise generation is reduced by on-chip termination, and low skew near-end outgoing signal echo cancellation. A test chip in a 0.35 micron digital CMOS technology uses these techniques for an eight bit wide single-ended voltage-mode simultaneous bidirectional interface and achieves a performance of 8 Gigabit per second per pin.

Further White Paper Details
Publisher	Sun Microsystems	File Format	PDF, requires Acrobat Rdr 5
Date Published	February 2002	Downloads	7
Format	White Papers
Topics	Interfaces / Buses / I/Os, ASICs - Chip Sets

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