RISC-Based Servers White Papers
A 56-Entry Instruction Reorder Buffer
Overview A speculative execution high-end PA-RISC CPU has two 28-entry out-of-order instruction reorder buffers (IRBs), one for alu/floating point operations and one for memory operations. The IRBs are capable of inserting any combination of four instructions per cycle. Each cycle, the IRBs launch up to four instructions for execution, two from the ALU IRB and two from the MEM IRB. Up to four instructions (two from each IRB) retire each cycle. The insert, launch and retire mechanisms of this out-of-order machine contain 850k transistors in 52.6mm˛. This white paper provides detailed information about the instruction reorder buffers.
| Publisher | Hewlett Packard | File Format | HTML |
|---|---|---|---|
| Date Published | October 2003 | Downloads | 24 |
| Format | White Papers | ||
| Topics | |||
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