Computer Testing Equipment White Papers
New Techniques for Testing Power Factor Correction Circuits
Overview This paper describes how to test the feedback loops in power factor correction (PFC) chips for stability. It discusses measurement techniques, stability guidelines, and loop bandwidth considerations for a range of manufacturers and integrated circuits (ICs), with emphasis on the new ICs developed recently. Stability testing is important because loop bandwidth and stability affect how fast the circuit will respond to source voltage transients and load changes. Power factor correction circuits often have two feedback loops. Both loops can have stability problems, and both loops can be tested for stability. One is a relatively slow loop that senses and sets the average output voltage. The other is a relatively fast loop that senses the instantaneous AC input voltage and tries to make the AC input current proportional to it. This second loop has a dynamically changing operating point and presents special measurement challenges. This paper describes procedures for testing both loops and gives guidelines and examples for several chips.
| Publisher | Venable Industries Inc. | File Format | HTML |
|---|---|---|---|
| Date Published | August 2003 | Downloads | 29 |
| Format | White Papers | ||
| Topics | |||
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