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A Bus Delay Reduction Technique Considering Crosstalk
Overview As the CMOS technology scaled down, the horizontal coupling capacitance between adjacent wires plays dominant part in wire load, crosstalk interference becomes a serious problem for VLSI design. We focused on delay increase caused by crosstalk. On-chip bus delay is maximized by crosstalk effect when adjacent wires simultaneously switch for opposite signal transition directions. This paper proposes a bus delay reduction technique by intentional skewing signal transition timing of adjacent wires. An approximated equation of bus delay shows our delay reduction technique is effective for repeater-inserted bus. The result of SPICE simulation shows that the total bus delay reduction by from 5% to 20% can be achieved.
| Publisher | Special Interest Group on Design Automation (SIGDA) | File Format | PDF, requires Acrobat Rdr 5 |
|---|---|---|---|
| Date Published | August 2003 | Downloads | 10 |
| Format | White Papers | ||
| Topics | |||
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