White Papers
Layout Compaction for Yield Optimization via Critical Area Minimization
Overview Throughout the manufacturing process of VLSI circuits many point defects can be introduced into the IC layers during the lithography stage. These point defects may be missing patterns that cause opens in the circuits, or extra patterns. This paper presents a new compaction algorithm to improve the yield of IC layout. The yield is improved by reducing the area where the faults are more likely to happen known as critical area. Instead of assuming that the critical area could probably be present everywhere in the layout, the algorithm first finds where this area can actually exist, and then attempts to minimize it. The algorithm takes benefit from a fast multi-layer critical area computation to extract the rectangles that compose it. Afterwards, the extracted rectangles are involved into the layer minimization process which is the second phase of the compaction procedure to minimize their area.
| Publisher | Special Interest Group on Design Automation (SIGDA) | File Format | PDF, requires Acrobat Rdr 5 |
|---|---|---|---|
| Date Published | August 2003 | Downloads | 1 |
| Format | White Papers | ||
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