Graphics Components White Papers
Synthesis of Parallel Hardware Implementations from Synchronous Dataflow Graph Specifications
Overview We present techniques for mapping applications specified in SDF to parallel digital hardware implementations. Two styles of architecture generation are described. They are a general resource sharing style for flexibility, and the mapping of sequenced groups for compact communication and interconnect. A design flow for hardware synthesis from SDF graphs is presented. In order to minimize cost while meeting performance requirements, we take advantage of opportunities for resource sharing at the coarse-grain task level. Since there are fewer task nodes than in a fine-grain or arithmetic representation of the task graph, determining a near-optimal partitioning is faster in our approach than in behavioral synthesis.
| Publisher | University of California, Berkeley | File Format | PDF, requires Acrobat Rdr 5 |
|---|---|---|---|
| Date Published | August 2003 | Downloads | 13 |
| Format | White Papers | ||
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