Packetized Voice White Papers
Analysis of a Packet Switch with Memories Running Slower Than the Line-Rate
Overview Essentially, the packet-switch performs packet-by-packet load balancing, or “inverse-multiplexing” over multiple independent packet-switches. Each lower-speed packet switch, operates at a fraction of the line-rate,; for example, if each packet-switch operates at rate no memory buffers are required to operate at the full line-rate of the system. Ideally, a PPS would share the benefits of an output-queued switch; i.e. the delay of individual packets could be precisely controlled, allowing the provision of guaranteed qualities of service. This paper asks about the possibility for a PPS to precisely emulate the behavior of an output-queued packet-switch with the same capacity and with the same number of ports. The main result of this paper is that it is theoretically possible for a PPS to emulate a FCFS output-queued packet-switch if each layer operates at a rate of approximately. This simple result is analogous to Clos theorem for a three-stage circuit switch to be strictly non-blocking. It is further shown that the PPS can emulate any QoS queueing discipline if each layer operates at a rate of approximately 3Rk.
| Publisher | Stanford Knowledgebase | File Format | PDF, requires Acrobat Rdr 5 |
|---|---|---|---|
| Date Published | December 1999 | Downloads | 9 |
| Format | White Papers | ||
| Topics | |||
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